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NJU3430 NJU3430 16-character 1-line dot matrix vfd controller driver16-character 1-line dot matrix vfd controller driver the NJU3430 is a dot matrix vfd (vacuum fluorescent display)the NJU3430 is a dot matrix vfd (vacuum fluorescent display) controller driver for 16-character 1-line with icon display.controller driver for 16-character 1-line with icon display. it contains character generator rom/ram, address counter, oscilla- it contains character generator rom/ram, address counter, oscilla- tion circuit, command register, icon display ram, high voltage drivers,tion circuit, command register, icon display ram, high voltage drivers, and serial interface circuit.and serial interface circuit. the display data or the command data is transmitted with the serial the display data or the command data is transmitted with the serial interface circuits.interface circuits. the character generator consists of 8,400 bits rom and 35 x 8 bits the character generator consists of 8,400 bits rom and 35 x 8 bits ram. the cg ram stores 8 kinds of character by 5 x 7dots maxi-ram. the cg ram stores 8 kinds of character by 5 x 7dots maxi- mum.mum. the 16-common and 37-segment (35 for character, 2 for icon) drivers the 16-common and 37-segment (35 for character, 2 for icon) drivers operated up to 45v drive the display of 16-character 1-line with 32-operated up to 45v drive the display of 16-character 1-line with 32- icon.icon. furthermore, the NJU3430 incorporates one output port which drives furthermore, the NJU3430 incorporates one output port which drives the led.the led. nn package outline package outline l l 16-character 1-line dot matrix vfd controller driver16-character 1-line dot matrix vfd controller driver l l serial interface with microprocessorserial interface with microprocessor l l display data ramdisplay data ram 16 x 8 bits16 x 8 bits : 16-character 1-line display: 16-character 1-line display l l character generator romcharacter generator rom 8,400 bits8,400 bits : 240 characters for 5 x 7 dots: 240 characters for 5 x 7 dots l l character generator ramcharacter generator ram 35 x 8 bits35 x 8 bits : 8 patterns (5 x 7 dots): 8 patterns (5 x 7 dots) l l icon display ramicon display ram 16 x 2 bits16 x 2 bits : maximum 32 icon: maximum 32 icon l l vfd driving voltagevfd driving voltage | v| v dddd -v-v fdpfdp | | 45v45v timing signaltiming signal : 16: 16 segment signalsegment signal : 35 (except for icon segment signal): 35 (except for icon segment signal) l l output port for led : 1output port for led : 1 l l display on/off functiondisplay on/off function l l digit scan functiondigit scan function l l display duty (contrast control) : 8-step (8/16 to 15/16)display duty (contrast control) : 8-step (8/16 to 15/16) l l character / icon shift functioncharacter / icon shift function l l display mode (9 to 16 digits)display mode (9 to 16 digits) l l oscillation circuit on-chip (external resistor and capacitor required)oscillation circuit on-chip (external resistor and capacitor required) l l operating voltageoperating voltage 3.0v to 5.5v (except vfd driving voltage)3.0v to 5.5v (except vfd driving voltage) l l package outlinepackage outline qfp 64qfp 64 l l c-mos technologyc-mos technology nn general description general description jul. 2003 ver. 3 nn features features NJU3430fg1NJU3430fg1
NJU3430 NJU3430 n n pin configuration pin configuration 1 1 7 3 2 3 3 4 8 4 9 6 4 s 5 s 6 s 7 s 9 s 8 s 1 0 s 1 2 s 1 1 s 1 3 s 1 4 s 1 5 s 1 6 s 1 7 s 1 9 s 2 0 s 1 8 s 2 1 s 2 2 s 2 3 s 2 4 s 2 5 s 2 6 s 2 7 s 2 8 s 2 9 s 3 0 s 3 1 s 3 2 s 3 3 s 3 4 s 3 5 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 v f d p v s s o s c 1 o s c 2 r s t c s c l k s i r s v d d p 1 m k 2 m k 1 s 1 s 2 s 3 s 4 n j u 3 4 3 0 1 6 n n block diagram block diagram s i c s c l k r s v s s o s c 1 o s c 2 v d d r s t v f d p m k 1 ~ m k 2 s 1 ~ s 3 5 p 1 t 1 ~ t 1 6 8 b i t s s h i f t r e g . i n s t r u c t i o n d e c o d e r t i m i n g g e n . c r o s c . s t a t e r e g . d i s p l a y c o n t r o l a d d r e s s s e l e c t o r r e a d a d d r e s s c o u n t e r l i n e a d d r e s s c o u n t e r t i m i n g d r i v e r d d r a m 1 6 x 8 b i t c g r o m 8 , 4 0 0 b i t p o r t d r i v e r c g r a m 3 5 x 8 b i t s e g m e n t d r i v e r m k r a m 1 6 x 2 b i t i c o n d r i v e r r e s e t
NJU3430 NJU3430 n n terminal description terminal description no. symbol i/o f u n c t i o n 57 v dd - power source : v dd =+3.0 to 5.5v 49 v ss - gnd : v ss =0v 48 v fdp - vfd driving power sourse v dd -20v to v dd -45v 50 osc 1 i cr oscillation terminal external r and c connect to these terminals. (target f osc =360khz) 51 osc 2 o 54 clk i serial clock input terminal the serial data input synchronizing the rise edge of this terminal. 53 cs i chip select terminal when the cs terminal is "h" the serial data input is not available. 55 si i serial data input terminal the data input is msb first. 56 rs i register selection signal input terminal rs="0" : instruction register rs="1" : data register 52 rst i reset terminal rst="l" : reset -each address -each ram data -display digits -contrast control -all display off -all outputs are "l" : (00) h : unfixed : 16-digit : 8/16 dury 61 to 64, 1 to 31 s 1 to s 35 o segment output terminals (internal pull-down resistance) 32 to 47 t 1 to t 16 o timing output terminals (internal pull-down resistance) 60 59 mk 1 mk 2 o icon output terminals (internal pull-down resistance) 58 p 1 o output port terminal this terminal is suitable for led.
NJU3430 NJU3430 n n function description function description (1)cg ram data and character dot matrix (1)cg ram data and character dot matrix the character generator ram (cg ram) stores any kinds of character pattern by 5 x 7 dots written by the user the character generator ram (cg ram) stores any kinds of character pattern by 5 x 7 dots written by the user program to display user?s original character pattern. the cg ram stores 8 kinds of character by 5 x 7 dots maximum. program to display user?s original character pattern. the cg ram stores 8 kinds of character by 5 x 7 dots maximum. to display user?s original character pattern stored in the cg ram, the address data (00)h - (07) should be written to display user?s original character pattern stored in the cg ram, the address data (00)h - (07) should be written to the dd ram as shown in table 2. to the dd ram as shown in table 2. character code (dd ram data) cg ram address correspondence of cg ram data and seg terminal ac5 ac4 ac3 ac2 ac1 ac0 sc4 sc3 sc2 sc1 sc0 (00) h 0 0 0 0 0 0 s 1 s 2 s 3 s 4 s 5 0 0 1 s 6 s 7 s 8 s 9 s 10 0 1 0 s 11 s 12 s 13 s 14 s 15 0 1 1 s 16 s 17 s 18 s 19 s 20 1 0 0 s 21 s 22 s 23 s 24 s 25 1 0 1 s 26 s 27 s 28 s 29 s 30 1 1 0 s 31 s 32 s 33 s 34 s 35 1 1 1 invalid address (01) h 0 0 1 0 0 0 s 1 s 2 s 3 s 4 s 5 0 0 1 s 6 s 7 s 8 s 9 s 10 0 1 0 s 11 s 12 s 13 s 14 s 15 0 1 1 s 16 s 17 s 18 s 19 s 20 1 0 0 s 21 s 22 s 23 s 24 s 25 1 0 1 s 26 s 27 s 28 s 29 s 30 1 1 0 s 31 s 32 s 33 s 34 s 35 1 1 1 invalid address : : : : : : : : : : : : (07) h 1 1 1 0 0 0 s 1 s 2 s 3 s 4 s 5 0 0 1 s 6 s 7 s 8 s 9 s 10 0 1 0 s 11 s 12 s 13 s 14 s 15 0 1 1 s 16 s 17 s 18 s 19 s 20 1 0 0 s 21 s 22 s 23 s 24 s 25 1 0 1 s 26 s 27 s 28 s 29 s 30 1 1 0 s 31 s 32 s 33 s 34 s 35 1 1 1 invalid address * when the data is written to cg ram successively, the invalid address is skipped automatically. * when the data is written to cg ram successively, the invalid address is skipped automatically. (ex.)cg ram address : (06) (ex.)cg ram address : (06) h h cg ram address : (08) cg ram address : (08) h h after data writing operation after data writing operation table 1.correspondence of cg ram address, dd ram character code table 1.correspondence of cg ram address, dd ram character code and cg ram character pattern(5 x 7 dots). and cg ram character pattern(5 x 7 dots).
NJU3430 NJU3430 table 2.cg rom character pattern (rom version -02) table 2.cg rom character pattern (rom version -02)
NJU3430 NJU3430 (2)reset function (2)reset function (2-1)initialization by reset terminal (2-1)initialization by reset terminal the NJU3430 incorporates rst terminal to initialize the all system. when the "l" level is input over 1us to the the NJU3430 incorporates rst terminal to initialize the all system. when the "l" level is input over 1us to the rst terminal, the reset sequence is executed. the initialization flow is shown below : rst terminal, the reset sequence is executed. the initialization flow is shown below : each ram address each ram address --- (00) --- (00) h h each ram data each ram data --- unfixed --- unfixed output port output port --- "l" level (v --- "l" level (v ss ss ) ) display digits display digits --- 16-digit --- 16-digit contrast control contrast control --- 8/16 duty --- 8/16 duty all display on/off all display on/off --- all display off --- all display off (2-2)initialization (after the reset) (2-2)initialization (after the reset) reset reset display digits set display digits set ? ? (initialization : 16-digit) (initialization : 16-digit) contrast control set contrast control set ? ? (initialization : 8/16 duty) (initialization : 8/16 duty) dd ram address set dd ram address set ? ? data writing data writing ? ? data set should be executed because data set should be executed because the data in dd ram is unfixed. the data in dd ram is unfixed. cg ram address set cg ram address set ? ? data writing data writing ? ? data set should be executed because data set should be executed because the data in cg ram is unfixed. the data in cg ram is unfixed. mk ram address set mk ram address set ? ? data writing data writing ? ? data set should be executed because data set should be executed because the data in mk ram is unfixed. the data in mk ram is unfixed. output port set output port set ? ? (initialization : all ?low? level) (initialization : all ?low? level) all display off all display off
NJU3430 NJU3430 (3)instruction (3)instruction each instruction is shown in the table 3. the data should be written to the ram continuously after the ram each instruction is shown in the table 3. the data should be written to the ram continuously after the ram address set. the order of data writing is msb first. address set. the order of data writing is msb first. table 3. table of instruction table 3. table of instruction instruction msb serial data lsb d e s c r i p t i o n rs b7 b6 b5 b4 b3 b2 b1 b0 maker test 0 0 0 0 0 0 0 0 0 output port set 0 0 0 0 0 0 0 1 p1 output port control display on/off 0 0 0 0 0 0 1 m d set the display on/off (character and icon) display duty set 0 0 0 0 0 1 d2 d1 d0 set the contrast control display shift 0 0 0 0 1 0 lr m d set the display shift (character and icon) display blink set 0 0 0 1 b2 b1 b0 m d set the blink interval (character and icon) display digits set 0 0 1 0 0 0 c2 c1 c0 set the display digits (9 to 16 degits) ram address set 0 1 0 0 0 ad3 ad2 ad1 ad0 set the ram address (ad0 to ad3 : dd ram) (am0 to am3 : mk ram) (ac0 to ac5 : cg ram) 0 0 1 am3 am2 am1 am0 1 ac5 ac4 ac3 ac2 ac1 ac0 write data to ram 1 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 after the ram address set, the data should be written to ram (sd0 to sd7 : dd ram) (sm0 to sm1 : mk ram) (sc0 to sc4 : cg ram) 0 0 0 0 0 0 sm1 sm0 0 0 0 sc4 sc3 sc2 sc1 sc0 *instruction is executed within 32us from the rise edge of the chip select cs signal. (at f *instruction is executed within 32us from the rise edge of the chip select cs signal. (at f osc osc =250khz) =250khz)
NJU3430 NJU3430 (3-1)description of each instruction (3-1)description of each instruction (a)maker testing (a)maker testing rs b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 set the test mode. set the test mode. (b)output port set (b)output port set rs b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 1 p1 set the output port (1 bit static operation)."p1" is output port name. set the output port (1 bit static operation)."p1" is output port name. *p1 does not drive vfd. *p1 does not drive vfd. p1 f u n c t i o n 0 "l" level is output. 1 "h" level is output. (c)display on/off (c)display on/off rs b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 1 m d set the display on/off (character and icon). all display are off after reset. set the display on/off (character and icon). all display are off after reset. m d f u n c t i o n 0 0 icon display "off", character display "off" 0 1 icon display "off", character display "on" 1 0 icon display "on", character display "off" 1 1 icon display "on", character display "on" (d)display duty set (d)display duty set rs b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 1 d2 d1 d0 one duty is selected from among eight kinds of duty by display duty set. 8/16 duty (lowest contrast) is set one duty is selected from among eight kinds of duty by display duty set. 8/16 duty (lowest contrast) is set after reset, an optional duty should be selected before display operation. after reset, an optional duty should be selected before display operation. b2 b1 b0 duty 0 0 0 8/16 0 0 1 9/16 : : : : 1 1 0 14/16 1 1 1 15/16
NJU3430 NJU3430 (e)display shift (e)display shift rs b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 1 0 lr m d the display positions of character and icon are shifted by display shift instruction. when the codes of "lr", "m" the display positions of character and icon are shifted by display shift instruction. when the codes of "lr", "m" and "d" mentioned below are written into "b2", "b1" and "b0", the display positions are shifted individually. and "d" mentioned below are written into "b2", "b1" and "b0", the display positions are shifted individually. lr f u n c t i o n 0 shift the display position to the right. 1 shift the display position to the left. m f u n c t i o n 0 the shift operation is not available. 1 the shift oparation is selected for icon. d f u n c t i o n 0 the shift operation is not available. 1 the shift oparation is selected for character. 16-digit display example 16-digit display example [input data] [correspondence of dd ram, mk ram address and display] [input data] [correspondence of dd ram, mk ram address and display] 00010001 00010001 (dd ram right shift) (dd ram right shift) 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 0f 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e ? ? mk ram mk ram ? ? dd ram dd ram 1-digit 8-digit 16-digit 1-digit 8-digit 16-digit 00010010 00010010 (mk ram right shift) (mk ram right shift) 0f 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f ? ? mk ram mk ram ? ? dd ram dd ram 00010011 00010011 (dd,mk ram right (dd,mk ram right shift) shift) 0f 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e ? ? mk ram mk ram ? ? dd ram dd ram 9-digit display example 9-digit display example [input data] [correspondence of dd ram, mk ram address and display] [input data] [correspondence of dd ram, mk ram address and display] 00010001 00010001 (dd ram right shift) (dd ram right shift) 00 01 02 03 04 05 06 07 08 0f 00 01 02 03 04 05 06 07 ? ? mk ram mk ram ? ? dd ram dd ram 1-digit 8-digit 1-digit 8-digit 00010010 00010010 (mk ram right shift) (mk ram right shift) 0f 00 01 02 03 04 05 06 07 00 01 02 03 04 05 06 07 08 ? ? mk ram mk ram ? ? dd ram dd ram 00010011 00010011 (dd,mk ram right (dd,mk ram right shift) shift) 0f 00 01 02 03 04 05 06 07 0f 00 01 02 03 04 05 06 07 ? ? mk ram mk ram ? ? dd ram dd ram *in spite of display digits, the data of 16-digit is required to write into dd ram. *in spite of display digits, the data of 16-digit is required to write into dd ram.
NJU3430 NJU3430 (f)display blink set (f)display blink set rs b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 1 b2 b1 b0 m d one blink state of character and icon is selected from among eight-step blink state by display blink set. non- one blink state of character and icon is selected from among eight-step blink state by display blink set. non- blink is selected after reset. the optional blink state should be selected before display operation. blink is selected after reset. the optional blink state should be selected before display operation. m f u n c t i o n 0 the blink operation is not available. 1 the blink oparation is selected for icon. d f u n c t i o n 0 the blink operation is not available. 1 the blink oparation is selected for character. b2 b1 b0 s t a t u s 0 0 0 non-blink 0 0 1 blink at about 0.1s : : : : 1 1 0 blink at about 0.6s 1 1 1 blink at about 0.7s *at f *at f osc osc =360khz =360khz (g)display digits set (g)display digits set rs b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 0 0 0 c2 c1 c0 the number of display digits is selected from among 9-digit to 16-digit by display digits set. 16-digit is selected the number of display digits is selected from among 9-digit to 16-digit by display digits set. 16-digit is selected after reset. the optional number of display digits should be selected before display operation. after reset. the optional number of display digits should be selected before display operation. c2 c1 c0 display digits 0 0 0 16-digit display 0 0 1 9-digit display : : : : 1 1 0 14-digit display 1 1 1 15-digit display
NJU3430 NJU3430 (h)ram address set (h)ram address set rs b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 0 0 ad3 ad2 ad1 ad0 1 0 0 1 am3 am2 am1 am0 1 1 ac5 ac4 ac3 ac2 ac1 ac0 the dd ram, mk ram and cg ram address are set by ram address set. correspondences of each ram the dd ram, mk ram and cg ram address are set by ram address set. correspondences of each ram address and display position are shown below : address and display position are shown below : ? ? dd ram addredd set:(00) dd ram addredd set:(00) h h to (0f) to (0f) h h ? ? mk ram address set:(00) mk ram address set:(00) h h to (0f) to (0f) h h ? ? cg ram address set:(00) cg ram address set:(00) h h to (3f) to (3f) h h dd ram address 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f digits 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 correspondence of dd ram address and timing terminals (not shift) correspondence of dd ram address and timing terminals (not shift) mk ram address 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f digits 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 correspondence of mk ram address and timing terminals (not shift) correspondence of mk ram address and timing terminals (not shift) about the detail of cg ram address, refer to "(1)cg ram data and character dot matrix?. about the detail of cg ram address, refer to "(1)cg ram data and character dot matrix?. (i)write data to ram (i)write data to ram rs b7 b6 b5 b4 b3 b2 b1 b0 1 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 0 0 0 0 0 0 sm1 sm0 0 0 0 sc4 sc3 sc2 sc1 sc0 the data are written into dd ram, mk ram and cg ram by write data to ram. the writing data address is the data are written into dd ram, mk ram and cg ram by write data to ram. the writing data address is used that is set the address just before writing data. therefore, when the new data writing, the address set should used that is set the address just before writing data. therefore, when the new data writing, the address set should be executed before writing data. the address is increased by 1 automatically after writing data, therefore, the mpu be executed before writing data. the address is increased by 1 automatically after writing data, therefore, the mpu writes the data into the each ram without any address setting after the start address. writes the data into the each ram without any address setting after the start address. ? ? dd ram data set:(00) dd ram data set:(00) h h to (ff) to (ff) h h ? ? mk ram data set:(00) mk ram data set:(00) h h to (03) to (03) h h ? ? cg ram data set:(00) cg ram data set:(00) h h to (1f) to (1f) h h (writing example) (writing example) 1byte 2byte 3byte 4byte 1byte 2byte 3byte 4byte 10000011 01010101 11111000 00110101 10000011 01010101 11111000 00110101 dd ram address dd ram address(03) dd ram address dd ram address(03) h h dd ram address(04) dd ram address(04) h h dd ram address(05) dd ram address(05) h h set(03) set(03) h h set cg rom(55) set cg rom(55) h h set cg rom(f8) set cg rom(f8) h h set cg rom(35) set cg rom(35) h h the writing data in the each ram are shown below. the writing data in the each ram are shown below. dd ram data[sd7 to sd0] dd ram data[sd7 to sd0] --- character code of each digit --- character code of each digit : (00) : (00) h h to (ff) to (ff) h h mk ram data[sm1 to sm0] mk ram data[sm1 to sm0] --- icon display of each digit --- icon display of each digit : sm1 : sm1 ? ? mk mk 2 2 , sm0 , sm0 ? ? mk mk 1 1 cg ram data[sc4 to sc0] cg ram data[sc4 to sc0] --- character code --- character code : (00) : (00) h h to (0f) to (0f) h h dot data dot data (about the detail, refer to "(1)cg ram data and character dot matrix?.) (about the detail, refer to "(1)cg ram data and character dot matrix?.)
NJU3430 NJU3430 n n interface with mpu interface with mpu the instruction and ram data are input through the serial port. the data form is 8-bit per word, and data transfer the instruction and ram data are input through the serial port. the data form is 8-bit per word, and data transfer is performed by synchronizing clock. the shift clock is input from external, and the data is loaded at the rising is performed by synchronizing clock. the shift clock is input from external, and the data is loaded at the rising edge of the shift clock. edge of the shift clock. one time transfer is executed by 8-bit unit. the transfer period is from falling edge to rising of the cs signal from one time transfer is executed by 8-bit unit. the transfer period is from falling edge to rising of the cs signal from external. therefore, when the rising edge of the cs signal is input, the operation is started. when more than 8-bit external. therefore, when the rising edge of the cs signal is input, the operation is started. when more than 8-bit data is input, the last 8-bit data is valid. data is input, the last 8-bit data is valid. the input data is judged as instruction or ram data by the rs signal at the rising edge of the cs signal (rs=?h? the input data is judged as instruction or ram data by the rs signal at the rising edge of the cs signal (rs=?h? : ram data, rs=?l? : instruction). when the input data is ram data, the ram address is increased one by one : ram data, rs=?l? : instruction). when the input data is ram data, the ram address is increased one by one automatically after data writing. automatically after data writing. c s c l k r s s i b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 m s b l s b 1 b y t e ( i n s t r u c t i o n ) m s b l s b 2 b y t e ( d a t a ) m s b l s b 3 b y t e ( d a t a ) s e l e c t t h e a d d r e s s c h a r a c t e r c o d e d a t a o f t h e n e x t a d d r e s s d d r a m w r i t i n g [ f o r e x a m p l e ] c h a r a c t e r c o d e d a t a n n absolute maximum ratings absolute maximum ratings note 1) if the lsi are used on condition above the absolute maximum ratings, the lsi may be destroyed. using the note 1) if the lsi are used on condition above the absolute maximum ratings, the lsi may be destroyed. using the lsi within electrical characteristics is strongly recommended for normal operation. use beyond the lsi within electrical characteristics is strongly recommended for normal operation. use beyond the electric characteristics conditions will cause malfunction and poor reliability. electric characteristics conditions will cause malfunction and poor reliability. note 2) decoupling capacitor should be connected between v note 2) decoupling capacitor should be connected between v dd dd and v and v ss ss , v , v fdp fdp and v and v ss ss due to the stabilized due to the stabilized operation for the lsi. operation for the lsi. note 3) all voltage values are specified as v note 3) all voltage values are specified as v ss ss = 0v. = 0v. the relation : v the relation : v dd dd > v > v ss ss , v , v dd dd > v > v ss ss 3 3 v v fdp fdp , v , v ss ss =0v must be maintained. =0v must be maintained. p a r a m e t e r symbol r a t i n g s unit c o n d i t i o n s supply voltage (1) v dd -0.3 to 6.5 v supply voltage (2) v fdp -40 to v dd +0.3 v input voltage v in -0.3 to v dd +0.3 v power dissipation p d 800 mw ta 25c qfp-64 storage temperature t stg -55 to 125 c operating temperature t opr -40 to 85 c output current i o1 -40 ma t 1 - t 16 i o2 -20 ma mk 1 - mk 2 i o3 -10 ma s 1 - s 35 i o4 -4.0 ma p 1 (led drive is available) total output current s i oh -100 ma all terminals at "h" level s i ol 100 ma all terminals at "l" level

NJU3430 NJU3430 - timing chart - timing chart c s c l k s i r s t c s u t c y c e t s i s u t s i h t s c t s c p w c s t c h t r s t r h v i h v i l v i h v i l v i h v i l v i h v i l v d d r s t s i t p r z t r s o n t r s o f f t r s l t r s l v i h v i l 0 . 8 v d d v s s v i h v i l 0 . 8 v d d t r t r 0 . 2 v f d p fig.1 data input timing fig.1 data input timing fig.2 reset timing fig.2 reset timing fig.3 output timing (cl=100pf, t fig.3 output timing (cl=100pf, t r r =20 to 80% or 80 to 20%) =20 to 80% or 80 to 20%)
NJU3430 NJU3430 n n vfd driving wave form vfd driving wave form o s c 1 t 1 t 2 t 3 t 1 6 s 1 t o s 3 5 m k 1 t o m k 2 t c y c e t b k t d g t s p : : oscillation frequency oscillation frequency : t : t cyce cyce minimum blanking time minimum blanking time : t : t bk bk =t =t cyce cyce x 4 x 4 (duty15/16) (duty15/16) 1-character display time 1-character display time : t : t dg dg =t =t bk bk x 16 x 16 1-cycle display time 1-cycle display time : t : t sp sp =t =t dg dg x digits x digits
NJU3430 NJU3430 n n application circuit application circuit 5 x 7 d o t m a t r i x v f d d i s p l a y a n o d e a n o d e g r i d h e a t e r v d d v d d v d d m k 1 - m k 2 s 1 - s 3 5 t 1 - t 1 6 m c u n j u 3 4 3 0 v s s o u t p u t p o r t r s t c s c l k s i r s v s s v f d p o s c 1 o s c 2 p 1 v f d p z d l e d
m e m o [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

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